As is well known, a growing trend in the manufacture of semiconductor integrated circuits is toward integration on a large and very large scale.
This involves increased technological commitment to produce circuit devices which can incorporate on a single chip a very large number (on the order of one million) of individual active components.
In such an application, there exists an evident demand for quality control and statistical analysis techniques which can result in readier identification of manufacturing process steps of specially critical value in the production of faultless circuits. All this in order to better aim the investigative effort at such critical process aspects, whenever required.
A prior technique directed to fill this demand has been the provision of test contact structures nested in the integrated circuit and adapted to be analysed electrically for quality control purposes. Such structures are specially suitable to pick up faults that have occurred during the contact opening process itself.
In essence, it is a matter for providing a long chain of contacts which alternately interconnect surface metallization layers and active areas of the circuit.
If the chain ends are biased electrically, a missed connection, for example, can be readily located by measuring the value of the current flowing through the structure.
A drastic decrease of the design value for that current would reveal a break in the chain of contacts.
However, this prior approach is ill adapted to implementation within integrated memory circuits, and especially within cells of the EPROM type, and in any case does not match the topography of such memories.
Such memory cells have, in fact, a special topography that would disallow formation of the above-noted contact chains unless some steps of the manufacturing process are changed to suit. This runs contrary, therefore, to the very objectives of such test contact structures, which are expected to enable troubleshooting of the customary steps of the process.